Advanced IC packaging is next front in the chip wars

Advanced IC packaging is a hot new source of competition among manufacturers of AI processors and other advanced integrated circuits (ICs), and emerging as the next front in the US government’s efforts to reduce America’s dependence on foreign suppliers and retard China’s technological progress.

However, unlike “front-end” IC wafer fabrication, where US sanctions have seriously constrained China’s advance, “back-end” assembly, packaging and test (APT) is an area where China has a large market presence and sophisticated technology, making it relatively immune to US technology blocks.

Taiwan’s TSMC, by far the world’s largest and most technologically advanced IC foundry, is rapidly expanding its Chip-on-Wafer-on-Substrate (CoWoS) packaging capacity. This will eliminate a bottleneck that has limited the supply of the latest AI processors from Nvidia, AMD and Intel fabricated at process nodes below 5 nanometers.

Huawei, which has so far been unable to move below 5nm due to the ban on selling ASML’s EUV lithography chip-making systems to China, has used its own IC design and packaging technology to move above the ceiling the US Commerce Department has put on the performance of Nvidia chips that can be sold there.

Specifically, Huawei’s new Ascend 910C processor, which could see commercial shipments within the next two months, reportedly outperforms Nvidia’s dumbed-down H20.

Tom’s Hardware writes, “According to Huawei, the device is on par with Nvidia’s H100, but it is unclear [on] which benchmark terms the Ascend 910C is comparable to Nvidia’s previous-generation flagship product.” ExtremeTech calculates that, overall, the H20 has “28% less AI performance” than the H100.

Even if Huawei is overstating its capability, it